A slide detailing the design of a new AMD processor geared toward the ultramobile market has surfaced, The slide depicts a processor, derived from the current AMD64 architecture, but stripped down to the bare essentials. It still has an integrated memory controller, although single-channel DDR2-400 or SODIMM, and relies on the HyperTransport bus systems for communicating with other components (16 lanes, 800MHz). The L2 cache has been reduced to 256KB, one 64KB L1 instruction cache and one 64KB L1 data cache.
When operating at 1GHz the entire package consumes a mere 8W. This is more than the mobile versions of VIA Nano and Intel Atom, but those are without the northbridge and memory controller. AMD has these on-die. The package measures 27x27mm (729mm2) and is of the BGA formfactor with 812 pins.
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